DKE German Commission for Electrical, Electronic & Information Technologies of DIN and VDE
DIN EN IEC 62433-6
; VDE 0847-33-6:2024-12
EMC IC modelling - Part 6: Models of integrated circuits for pulse immunity behavioural simulation - Conducted pulse immunity modelling (ICIM-CPI) (IEC 62433-6:2020); German version EN IEC 62433-6:2020
EMV-IC-Modellierung - Teil 6: Modelle integrierter Schaltungen für die Simulation des Verhaltens bei Störfestigkeit gegen Impulse - Modellierung der Störfestigkeit gegen leitungsgeführte Impulse (ICIM-CPI) (IEC 62433-6:2020); Deutsche Fassung EN IEC 62433-6:2020
Overview
This part of the DIN EN 62433 series of standards (VDE 0847-33) specifies a procedure for deriving a macro model that can be used to simulate the immunity of an integrated circuit (IC) to transient conducted disturbances such as electrostatic discharge (ESD) and fast transient electrical disturbances (EFT). This model is commonly called "Integrated Circuit Immunity Model Conducted Pulse Immunity", ICIM-CPI and is used to predict immunity levels to conducted pulse disturbances at IC terminal pins. The approach described is suitable for modelling analogue, digital and mixed-signal ICs. Several terminals of an IC can be part of a single model (such as input, output and supply pins). This document consists of two main parts: the first part is the electrical description of the elements of the ICIM-CPI macro model; the second part proposes a universal data exchange format called PIML, which is based on XML. This format provides for a usable and general form of ICIM-CPI coding for the simulation of immunity. Integrated circuits (ICs) used in the control systems of large and complex plants are increasingly subject to electronic interference from pulses that enter the integrated circuit via the IC terminal pins. Damage or even functional failures can be avoided if the immunity level against conducted impulse disturbances can be accurately predicted. This document specifies a procedure for deriving a macro model that can be used to simulate the immunity of an integrated circuit to transient conducted disturbances.